WZTOE Coding Guide for WIZwiki-W7500

WIZwiki_W7500

wizwiki_W7500

  • WIZnet W7500
  • 32-bit ARM Cortex-M0
  • 128KB Flash / 48 SRAM
  • Hardware TCP/IP coe (WIZnet TCP/IP Engine)
  • 64TQFP( 7x7mm)

  • CMSIS-DAP

  • SWD Con.

  • WIZwiki-W7500 feature

  • Arduino Pin compatible

  • ISP / SD Slot / REG LED
  • Ethernet PHY

HW : MII Interface

MII Interface
* WZTOE Signals

W7500_WZTOE Ethernet PHY
PD_00 CRS
PD_01 RXDV
PD_02 RXD0
PD_03 RXD1
PD_04 RXD2
PD_06 RXD3
PB_04 TXEN
PB_05 COL
PB_07 RXCLK
PB_08 DUP
PB_09 TXCLK
PB_10 TXD0
PB_11 TXD1
PB_12 TXD2
PB_13 TXD3
  • MDIO via GPIO

    Management Data Input/Output (MDIO), also known as Serial Management Interface (SMI) or Media Independent Interface Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface, or MII. The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits.
    http://en.wikipedia.org/wiki/Management_Data_Input/Output

  • PB_14 — MDIO (@IC+101)

  • PB_15 — MDC (@IC+101

SW : (will update code location)

  • ioLibary :“Internet Offload Library” for WIZnet chip. It includes drivers and application protocols.
    $\W7500_FW\Projects\Peripheral_Examples\WZTOE\ioLibrary

  • MDIO via GPIO: It Includes the MDIO Read and Write functions.
    $\W7500_FW\Projects\Peripheral_Examples\WZTOE\ioLibrary\MDIO\W7500x_miim.h
    $\W7500_FW\Projects\Peripheral_Examples\WZTOE\ioLibrary\MDIO\W7500x_miim.c

  • W7500 WZTOE (WIZnet TCPIP Engine) Driver
    $\W7500_FW\Libraries\W7500x_stdPeriph_Driver\inc\W7500x_WZTOE.h
    $\W7500_FW\Libraries\W7500x_stdPeriph_Driver\src\W7500x_WZTOE.c

Coding Guides

  • To use accurate Ticker of 1usec, set WZ100US value according to main clock(HCLK)
/* Set WZ_100US Register */
setTIC100US((GetSystemClock()/10000));
//getTIC100US();
//printf(" GetSystemClock: %X, getTIC100US: %X, (%X) rn",
// GetSystemClock, getTIC100US(), *(uint32_t *)TIC100US);
  • To clear Interrupt register, use Interrupt Clear Register (ICR) , Socket Interrupt Clear Register(Sn_ICR).
setSn_IMR(socket_number, interrupt_mask_bits);
...
socket_interrupt_state = getSn_IR(socket_number);
...
socket_interrupt_state = setSn_ICR(socket_number, interrupt_clear_bit);
  • To use previous codes, setSn_ICR() is warped by setSn_IR().

  • How to access WZTOE
    Memory map of TOE memory

  • Registers

#define WZTOE_COMMON_REGISTER_BASEADDR (0x4100_0000)
#define WZTOE_SOCKET_REGISTER_BASEADDR(sock_num) (0x4101_0000 + (sock_num)<<18))

/* Write to wztoe common register with offset address of 3 */
offset_addr = 3;
*(volatile uint32_t *)(WZTOE_COMMON_REGISTER_BASEADDR + offset_addr) = 0x12;

/* Read to wztoe socket 3 register with offset address of 8 */
sock_num = 3;
offset_addr = 8;
val = *(volatile uint32_t *)(WZTOE_SOCKET_REGISTER_BASEADDR(sock_num) + offset_addr)
  • TX/RX Buffer
    Cortex-m0 is able to access by 32-bits address. However, Sn_TX_WR(Socket n TX Write Pointer Register) and Sn_RX_RD (Socket n RX Read Pointer Register) is only the lower 16 bits of the pointer. Hence, to calcurate the address boundary, offset address shoud be masked by 0xFFFF.
#define WZTOE_SOCKET_TXBUF_BASEADDR(sock_num) (0x4102_0000 + (sock_num)<<18))
#define WZTOE_SOCKET_RXBUF_BASEADDR(sock_num) (0x4103_0000 + (sock_num)<<18))

/* Write to wztoe TX buffer with offset address of 3 */
sock_num = 3;
offset_addr = 0x0001_0000;
*(volatile uint32_t *)(WZTOE_SOCKET_TXBUF_BASEADDR(sock_num) + (offset_addr&0xFFFF)) = 0x12;

/* Read to wztoe RX buffer with offset address of 8 */
sock_num = 2;
offset_addr = 8;
val = *(volatile uint32_t *)(WZTOE_SOCKET_RXBUF_BASEADDR(sock_num) + (offset_addr&0xFFFF)
  • API for TX/RX Buffer
void WIZCHIP_READ_BUF (uint32_t BaseAddr, uint32_t ptr, uint8_t* pBuf, uint16_t len)
{
uint16_t i = 0;
WIZCHIP_CRITICAL_ENTER();

for(i = 0; i < len; i++)
pBuf[i] = *(volatile uint8_t *)(BaseAddr +((ptr+i)&0xFFFF));

WIZCHIP_CRITICAL_EXIT();
}

void WIZCHIP_WRITE_BUF(uint32_t BaseAddr, uint32_t ptr, uint8_t* pBuf, uint16_t len)
{
uint16_t i = 0;
WIZCHIP_CRITICAL_ENTER();

for( i=0; i<len; i++)
*(volatile uint8_t *)(BaseAddr + ((ptr+i)&0xFFFF)) = pBuf[i];

WIZCHIP_CRITICAL_EXIT();
}

void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
{
uint32_t ptr = 0;
uint32_t sn_tx_base = 0;

if(len == 0) return;
ptr = getSn_TX_WR(sn);
sn_tx_base = (TXMEM_BASE) | ((sn&0x7)<<18);
WIZCHIP_WRITE_BUF(sn_tx_base, ptr, wizdata, len);
ptr += len;
setSn_TX_WR(sn,ptr);
}

void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
{
uint32_t ptr = 0;
uint32_t sn_rx_base = 0;

if(len == 0) return;
ptr = getSn_RX_RD(sn);
sn_rx_base = (RXMEM_BASE) | ((sn&0x7)<<18); WIZCHIP_READ_BUF(sn_rx_base, ptr, wizdata, len); ptr += len; setSn_RX_RD(sn,ptr); } ``` ### MDIO via GPIO * Port Init. ```cpp /* Set GPIOs for MDIO and MDC */ GPIO_InitTypeDef GPIO_InitDef; GPIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO; GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT; GPIO_Init(GPIOx, &GPIO_InitDef); PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1); PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1); ``` * MDIO APIs ```cpp uint32_t link(void) { return ((mdio_read(GPIOB, PHYREG_STATUS)>>SVAL)&0x01);
}

void set_link(SetLink_Type mode)
{
uint32_t val=0;
assert_param(IS_SETLINK_TYPE(mode));

if( mode == CNTL_AUTONEGO)
{
val = CNTL_AUTONEGO;
}
else
{
val = (mode & (CNTL_SPEED|CNTL_DUPLEX));
}

mdio_write(GPIOB, PHYREG_CONTROL, val);

}
  • MDIO Read/Write Functions
void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)
{
for(val <<= (32-n); n; val<<=1, n--)
{
if(val & 0x80000000)
GPIO_SetBits(GPIOx, MDIO);
else
GPIO_ResetBits(GPIOx, MDIO);

delay(1);
GPIO_SetBits(GPIOx, MDC);
delay(1);
GPIO_ResetBits(GPIOx, MDC);
}
}

uint32_t input_MDIO( GPIO_TypeDef* GPIOx )
{
uint32_t i, val=0;
for(i=0; i<16; i++)
{
val <<=1;
GPIO_SetBits(GPIOx, MDC);
delay(1);
GPIO_ResetBits(GPIOx, MDC);
delay(1);
val |= GPIO_ReadInputDataBit(GPIOx, MDIO);
}
return (val);
}

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